Max speed of capture of analog data

I agree that you can calculate the PCIe and DDR II bandwidth easily. Based on the following comment.

"The COBRA Digitizer boards digitize the downconverter output (500MHz to 1GHz) at a 1GHz clock frequency to 2-bits of resolution. The digitizer ICs internally demultiplex this data by two producing 4-bits at 500MHz. ECL logic on the digitizer module then demultiplex this further to 32-bits at 62.5MHz, and then convert the data the CMOS/TTL logic levels. The CMOS/TTL data is then received by the digitizer board FPGAs (field programmable gate arrays)."

It seems like the ADC used presents the data to the FPGA at a rate of 62.5MHz at CMOS/TTL levels. The Altera devices can handle data rates much faster than that. Depending on the IO standard used you can expect the FPGA to receive data at rates up to 1 Gbps per single IO. It all depends on the IO standard of the ADC. I am not familiar with the ADCs used in this sort of application. But, the "digitizer" manufacturers generally design their high-end ADCs to hook up to FPGAs.

Hope this helps.