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New ContributorMax II EPM240T100C5N CLCD
I'm using an Altera MAX II EPM240T100C5N CPLD and trying to implement UART transmission using Verilog (bit-banged at 9600 baud). The design is written and successfully compiled in Quartus, and programmed to the board using the USB-Blaster. However, I do not see any signal on the TX pin when monitoring with an oscilloscope or picoscope.
And also without bit bang approach is there any direct configuration of transmitter and receiver for this board is available or not?
9 Replies
FvMSuper Contributor
Hi,
the term bit-banging doesn't seem to make sense for UART implementation in FPGA. It's commonly used for microcontroller implementations without hardware UART controller.In FPGA, UART is implemented in logiccells and registers, no matter if you import third party UART IP or write your own hardware description.
You may want to show your Verilog code to let others check why it's not working.
srimathiHi,
Thanks for your clarification. I'm still new to working with the Altera MAX II CPLD and Verilog in general.If you have any sample UART transmitter and receiver code, I'd really appreciate it if you could share it. It would help me understand the implementation better.
Thanks again for your support!
_AK6DN_Frequent Contributor
Look here: https://opencores.org/
Browse PROJECTS and COMMUNICATION CONTROLLERS and look for projects with UART in the name.
There are a bunch, from very simple to complex.
Most have been tested in actual FPGAs.
Farabi_AlteraRegular Contributor
Hello,
You will in UART IP to implement the design. Do you have the IP?
regards
Farabi
- srimathi
Hi,
I don't have anything like that(UART IP) and also no idea about it. Can you please share your thoughts on how to do the UART communication.
Thanks.
- Farabi_Altera
Hello,
Please refer to design example link provided by AK6DN. It will be helpful for your project.
regards,
Farabi
- FvM
Hi,
appended an example of simple UART RX/TX unit. Special feature is non standard bit sampling divider of 13 to achieve standard baud rates with 6/12/24 MHz clock.- srimathi
Hi,
I'm working in Verilog code, If you have that means it will be helpful.
