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srimathi's avatar
srimathi
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1 year ago

Max II EPM240T100C5N CLCD

I'm using an Altera MAX II EPM240T100C5N CPLD and trying to implement UART transmission using Verilog (bit-banged at 9600 baud). The design is written and successfully compiled in Quartus, and progra...
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Programmable Logic Device
FvM's avatar
FvM
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1 year ago

Hi,
the term bit-banging doesn't seem to make sense for UART implementation in FPGA. It's commonly used for microcontroller implementations without hardware UART controller.

In FPGA, UART is implemented in logiccells and registers, no matter if you import third party UART IP or write your own hardware description.

You may want to show your Verilog code to let others check why it's not working.

  • srimathi's avatar
    srimathi
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    1 year ago

    Hi,
    Thanks for your clarification. I'm still new to working with the Altera MAX II CPLD and Verilog in general.

    If you have any sample UART transmitter and receiver code, I'd really appreciate it if you could share it. It would help me understand the implementation better.

    Thanks again for your support!

    • _AK6DN_'s avatar
      _AK6DN_
      Icon for Frequent Contributor rankFrequent Contributor
      1 year ago

      Look here: https://opencores.org/

      Browse PROJECTS and COMMUNICATION CONTROLLERS and look for projects with UART in the name.

      There are a bunch, from very simple to complex.

      Most have been tested in actual FPGAs.

      • srimathi's avatar
        srimathi
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        1 year ago

        Grateful for the help, will check there.