Forum Discussion

srimathi's avatar
srimathi
Icon for New Contributor rankNew Contributor
1 year ago

Max II EPM240T100C5N CLCD

I'm using an Altera MAX II EPM240T100C5N CPLD and trying to implement UART transmission using Verilog (bit-banged at 9600 baud). The design is written and successfully compiled in Quartus, and progra...
Board Debug
Programmable Logic Device
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
appended an example of simple UART RX/TX unit. Special feature is non standard bit sampling divider of 13 to achieve standard baud rates with 6/12/24 MHz clock.

  • srimathi's avatar
    srimathi
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi,

    I'm working in Verilog code, If you have that means it will be helpful.