m25p26

It could be a good idea to check the signals on the flash with an oscilloscope to see if there is any hardware problem. You can also configure the FPGA with an SFL image and try to access the flash through the JTAG connector.

I have seen that instead of a clean external clk of 50 MHz, I have a clk of 1KHz. I'm confused because the circuit apparently seems correct. I attach the schematic, If anyone can help I would be grateful. Thanks.

i also would start with a simpler design. the Sources and Probes function can be useful during board bring up

The problem in the clock seems fixed, there was a short circuit between the case of the oscillator and one of his path. Now I have tried to configure the flash and the fpga with the jic file, but without success. I think something is wrong in the AS interface. I also have run succesfully the source&probe test with a switch and one led.

I have measured with the scope some pins, for example in nCE appears a voltage of 0.8v and in nSTATUS 1.8V, nCONFIG 2.5v and CONF_DONE 2.5V. The banks of the fpga are fed by 2.5v. Also I have probed the SFL design and the flash doesn`t configure with the jam file (no device id identification). I attach two captures with the logic analyzer in the AS interface. The first one when I plug in the board and it tries to configure itself, and the second one when I try to configure the flash via the SFL driver.

Do you ever have anything on the DATA0 signal? It's strange that the flash never replies anything. It could be interesting to probe both terminals of the 25 Ohm resistor with an oscilloscope.

There was a short circuit in the schottky array diodes, now the flash can be programmed through the JTAG and the AS interface. The next challenge is making nios run properly in the board, because when I configure it through eclipse it says Downloading to memory but verification failed between the address corresponding to the DDR memory. I will check the paths to the memory. At least the "hello world" example with on-chip memory works.

Now the program is downloaded into the ddr and the verification is ok but

You can try and create a design with a big on-chip memory for the CPU and run a memory test program from there. In Eclipse when you create a project, you have a memory test template that you can use, just ensure that the BSP is defined to only use the onchip memory for everything (text, bss, stack, heap...). You'll also probably have to turn on optimisations and use the small C library to make everything fit in the on-chip memory.

I have just run the mem test but after filling the start and the end address ( all the ddr memory region and only parts of it) the program stops and nothing appears.