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Altera_Forum
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14 years ago

m25p26

Hi everybody, I have finished a pcb design with a cyclone III Ep3c25q240, it is configurated in AS mode. There are two connector (10 pins), one for the JTAG and the other for the AS. When I dow...
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Altera_Forum
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14 years ago

When I try to debug the ddr commands with signaltap, some illegal and missing sources appear:

basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_cas_n

basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_ras_n

basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_we_n

" DDIO I/O pins cannot be tapped directly. Tap the hi/lo channels separately."

and

basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_cke

basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_cs_n

"The pre-synthesis tap must be preserved by Analysis & Synthesis before it can be tapped. Set the partition's netlist type to Source and recompile."