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Altera_Forum
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14 years ago

m25p26

Hi everybody, I have finished a pcb design with a cyclone III Ep3c25q240, it is configurated in AS mode. There are two connector (10 pins), one for the JTAG and the other for the AS. When I dow...
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Altera_Forum
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14 years ago

Now the program is downloaded into the ddr and the verification is ok but

it appears an error with the jtag debug (m_state = STATE_DEBUG failed).

Is there any method to check the ddr good-working? I'm using a SAMSUNG k4h561638n-lccc instead of a k4h561638f-tccc, which timing presets come in the ddr-controller altera megafunction. Maybe with a logic analyzer... but it would be a hard work taking from the board all the signals.

Many thanks,

ifdm