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Altera_Forum
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14 years ago

m25p26

Hi everybody, I have finished a pcb design with a cyclone III Ep3c25q240, it is configurated in AS mode. There are two connector (10 pins), one for the JTAG and the other for the AS. When I dow...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I have no experience with DDR memories unfortunately so I can't help you there.

With SignalTAP you can at least check if the DDR controller is stalling the CPU with the waitrequest signal.

Did you check the I/O timing constraints, and that timequest doesn't complain about timing?

Altera also has a memory interface debugging document (http://www.altera.com/literature/hb/external-memory/emi_debug_hw.pdf), you may find ideas there.