Honored Contributorin the timing diagram ,data0,data1,data2,data3 are the input data for the ram ,and there are output data,we,oe2 is the write and read signal respectly? but there is no reset signal? I wonder how the addr can be reset,since there is no reset signal . Anybody knows?
Honored ContributorUsually you don't need to reset the input signal to a RAM (or any other digital circuit).
Just change it when needed. If you don't want to carry any more read operations use the signals that enables and disable the whole memory.Honored ContributorI mean how the address of the ram can be generated,since there is no reset signal,how could i get the addr reset on start?
Honored ContributorI am not sure what you are actually referring to but it is you, the designer, who should generate the address as required.
Honored ContributorHonored ContributorI mean the addr should be 0,1,2,3.....
but there is no reset signal ,which signal could i use to determine the addr 0? when i have reset signal,i can set addr to 0 when the reset is low.So what can i do?Honored ContributorThe memory address is not generated by the memory. It is generated by some external circuitry... a processor, or maybe a counter or something. You would reset the processor or counter to start generating addresses at '0'. Those have reset inputs.
Honored ContributorNO,this module contains a ram and a control circuit,so it is generated by this module.
Honored ContributorHonored ContributorEither:
1) it is a ram (random access memory), meaning you have external access to the memory address lines (in which case your external control of these lines is what needs to be reset, not the ram), Or: 2) it is not a ram (and you need to ask a more precise question).
