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Altera_Forum
Honored Contributor
Honored ContributorIs every module need a reset signal?
in the timing diagram ,data0,data1,data2,data3 are the input data for the ram ,and there are output data,we,oe2 is the write and read signal respectly? but there is no reset signal? I wonder how the...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I mean how the address of the ram can be generated,since there is no reset signal,how could i get the addr reset on start? --- Quote End --- Sorry but I don't understand your question. Why don't you try providing a more detailed description of what you want to do? Whic FPGA you want to use, is the RAM internal or external, which RAM are you using, to do what, etc.
