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Altera_Forum
Honored Contributor
Honored ContributorIs every module need a reset signal?
in the timing diagram ,data0,data1,data2,data3 are the input data for the ram ,and there are output data,we,oe2 is the write and read signal respectly? but there is no reset signal? I wonder how the...
Altera_ForumHonored Contributor
Honored ContributorI mean the addr should be 0,1,2,3.....
but there is no reset signal ,which signal could i use to determine the addr 0? when i have reset signal,i can set addr to 0 when the reset is low.So what can i do?
