Altera_ForumHonored Contributor15 years agoIs every module need a reset signal? in the timing diagram ,data0,data1,data2,data3 are the input data for the ram ,and there are output data,we,oe2 is the write and read signal respectly? but there is no reset signal? I wonder how the...Show More未命名.jpg54 KB
Altera_ForumHonored Contributor15 years agoNO,this module contains a ram and a control circuit,so it is generated by this module.
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