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Altera_Forum's avatar
Altera_Forum
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15 years ago

Is every module need a reset signal?

in the timing diagram ,data0,data1,data2,data3 are the input data for the ram ,and there are output data,we,oe2 is the write and read signal respectly? but there is no reset signal? I wonder how the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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this module contains a ram and a control circuit

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Unfortunately you didn't provide any information about operation and intended purpose of "this module". Possibly it relies on FPGA power on reset, but yes, in many cases it's better to have an explicite reset for reliable operation.