Increase input delay on clock pin - Cyclone 2

Hi dipling,

--- Quote Start ---

Hi,

I have a clock connected to the P2 pin (CLK2 pin) and I need to delay it with one extra nanosecond.

--- Quote End ---

You should use a PLL for generating clocks with a skew wrt a reference clock. PLL's can be added by the MegaWizard in your design.

Hope this helps...

Hi,

PLL is not an option.. the same structure will be replicated about 8 times in the design and I don't have that many PLLs, actually I have none available at the moment. Thanks for sugestion anyways!

The I/O programmable delay configuration is available at the Assignment Editor.

But I'm not sure it would be the best solution. Why you need that delay? What exactly you want to achieve?

You mention you need it on eight different pins. What is the relation between those 8 signals? Are they 8 different clocks?

--- Quote Start ---

The I/O programmable delay configuration is available at the Assignment Editor.

--- Quote End ---

Yes, I found three options related to delays: D1 Fine Delay, D4 Fine Delay and DPCLKp to Fan-Out destinations delay. The first two have no effect (maybe because they can't be applied to this pin????) and the last one can't be used since this pin is not a Dual-Purpose clock pin.

--- Quote Start ---

Why you need that delay? What exactly you want to achieve?

--- Quote End ---

Have a look in the post attached image... I have a 1ns tSU parameter for the external device and source synchronous edge-aligned DDR input data. I thought that with a bit more delay on the clock line these settings could actually work...

I assumed that by constraining tSU, Quartus would enable the delay paths automatically, but it doesn't.

--- Quote Start ---

You mention you need it on eight different pins. What is the relation between those 8 signals? Are they 8 different clocks?

--- Quote End ---

Yes, all are independent unrelated clocks in range 2.5-125 Mhz.

--- Quote Start ---

Yes, I found three options related to delays: D1 Fine Delay, D4 Fine Delay and DPCLKp to Fan-Out destinations delay.

--- Quote End ---

I think these options are not supported in Cyclone families. The relevant options should be "increase/decrease input delay ...". But again, usually it is best to let the fitter manage those delays using the right timing constraints.

--- Quote Start ---

I have a 1ns tSU parameter for the external device and source synchronous edge-aligned DDR input data... Yes, all are independent unrelated clocks in range 2.5-125 Mhz.

--- Quote End ---

Multiple fast edge-aligned DDR input interfaces, without PLL, doesn't sound easy.

Either way, I'm not sure you are applying the right timing constraints. tSU as an output parameter, normally means clock-to-data delay, and not data-to-clock delay.