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The I/O programmable delay configuration is available at the Assignment Editor.
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Yes, I found three options related to delays: D1 Fine Delay, D4 Fine Delay and DPCLKp to Fan-Out destinations delay. The first two have no effect (maybe because they can't be applied to this pin????) and the last one can't be used since this pin is not a Dual-Purpose clock pin.
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Why you need that delay? What exactly you want to achieve?
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Have a look in the post attached image... I have a 1ns tSU parameter for the external device and source synchronous edge-aligned DDR input data. I thought that with a bit more delay on the clock line these settings could actually work...
I assumed that by constraining tSU, Quartus would enable the delay paths automatically, but it doesn't.
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You mention you need it on eight different pins. What is the relation between those 8 signals? Are they 8 different clocks?
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Yes, all are independent unrelated clocks in range 2.5-125 Mhz.
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