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Altera_Forum
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16 years ago

Increase input delay on clock pin - Cyclone 2

Hi, I am currently working on a Cyclone 2 ep2c35F672c6 FPGA and I don't find a solution to the following problem: I have a clock connected to the P2 pin (CLK2 pin) and I need to delay it ...
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Altera_Forum
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16 years ago

Hi,

PLL is not an option.. the same structure will be replicated about 8 times in the design and I don't have that many PLLs, actually I have none available at the moment. Thanks for sugestion anyways!