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Altera_Forum
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16 years ago

Increase input delay on clock pin - Cyclone 2

Hi, I am currently working on a Cyclone 2 ep2c35F672c6 FPGA and I don't find a solution to the following problem: I have a clock connected to the P2 pin (CLK2 pin) and I need to delay it ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

The I/O programmable delay configuration is available at the Assignment Editor.

But I'm not sure it would be the best solution. Why you need that delay? What exactly you want to achieve?

You mention you need it on eight different pins. What is the relation between those 8 signals? Are they 8 different clocks?