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Yes, I found three options related to delays: D1 Fine Delay, D4 Fine Delay and DPCLKp to Fan-Out destinations delay.
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I think these options are not supported in Cyclone families. The relevant options should be "increase/decrease input delay ...". But again, usually it is best to let the fitter manage those delays using the right timing constraints.
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I have a 1ns tSU parameter for the external device and source synchronous edge-aligned DDR input data... Yes, all are independent unrelated clocks in range 2.5-125 Mhz.
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Multiple fast edge-aligned DDR input interfaces, without PLL, doesn't sound easy.
Either way, I'm not sure you are applying the right timing constraints. tSU as an output parameter, normally means clock-to-data delay, and not data-to-clock delay.
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