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Honored Contributorif statment issue
hello i am a newbie at vhdl as well as say programming. I am facing issue which is very minor for u all to decide
consider i have a std_logic_vector 35 bits long and i want to check whether its 33 and 32 bits are 00 or 01 and so on... how do i check it? like this? if (din0(33 downto 32) = "00") then bla bla bla... right? if this is so i am getting an error for that :( why so help me out guys... i kknow its pretty simple but i cant do it...9 Replies
Altera_Forumthanks trickly. lets try and do it...
- Altera_Forum
The clock is needed if you want any registers. FPGA logic is based on clocks, so yes it is recommended you use clocks for ALL your designs. It will make your life much easier.
- Altera_Forum
Does this mean that i have to use clock in any code htat i write? I thoguht its just a simple code and assingment of inputs to outputs...
- Altera_Forum
Or try google: https://www.google.com/search?hl=en&q=vhdl+tutorial
- Altera_Forum
The Designer's Guide to VHDL (Systems on Silicon) by Peter J. Ashenden is supposed to be a good book. The cook book is pretty good as a quick guide (but not much detail).
But try browsing your library for VHDL books. - Altera_Forum
Tricky also plz refer to me any good starting guide or sort of book where from i can learn these basic things. I have the VHDL cookbook but it isnt exactly telling me all these details. I am lacking time and if this thing goes on like this, I wont be able to compelte a single lab /............... Pathetic and pitiful... shame on me being an engineer :(
- Altera_Forum
the problem is din0'length is 35
35-1 = 34. So you're asking for (34 downto 32), which is 3 bits not 2. Also, you are missing a load of signals from your process sensitivity list. This code will not simulate at all. And why are you not using the clock? This code is going to create latches (which are bad). - Altera_Forum
I am trying to build a 4x4 cross bar which i will use in a switch datapth. Here is the cross bar code:
library ieee; use ieee.std_logic_1164.all; entity cross_bar is port( -- clk,rst : in std_logic; din0,din1,din2,din3 : in std_logic_vector(34 downto 0); grant0,grant1,grant2,grant3 : in std_logic_vector(1 downto 0); dout0,dout1,dout2,dout3 : out std_logic_vector(34 downto 0) -- req0,req1,req2,req3 : out std_logic_vector(1 downto 0) ); end cross_bar; architecture cross_arc of cross_bar is begin process begin if (din0(din0'length-1 downto 32) = "00") then if (grant0 = "00") then dout0 <= din0; elseif (grant1 = "01") then dout1 <= din0; elseif (grant2 = "10") then dout2 <= din0; else (grant3 = "11") then dout3 <= din0; end if; end if; end process; end cross_arc; I am mad. Cant figure it out from last 2 hours. :( - Altera_Forum
Post more of your code. A single line snippet doesnt really help, because it doesnt show where the if is (it should be inside a process).
