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Altera_Forum
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14 years ago

if statment issue

hello i am a newbie at vhdl as well as say programming. I am facing issue which is very minor for u all to decide consider i have a std_logic_vector 35 bits long and i want to check whether its...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Tricky also plz refer to me any good starting guide or sort of book where from i can learn these basic things. I have the VHDL cookbook but it isnt exactly telling me all these details. I am lacking time and if this thing goes on like this, I wont be able to compelte a single lab /............... Pathetic and pitiful... shame on me being an engineer :(