Agilex 5 E-Series LVDS : Camera Link RX x7 (75 MHz / 525 Mbps) Data Rate Specification

Hello. Thank you for your help.

I am planning to implement an LVDS receiver using an Agilex 5 E-Series FPGA.

The specific requirements are as follows:

Camera Link Rx, LVDS Rx SERDES factor: x7

Clock rate: 75 MHz

Data rate: 525 Mbps, calculated as 75 MHz x7

I am checking the following section of the Agilex 5 E-Series datasheet:

LVDS SERDES Specifications

https://docs.altera.com/r/docs/813918/current/agilex-5-fpgas-and-socs-device-data-sheet/lvds-serdes-specifications

Table 64. E-Series Device Group B FPGAs LVDS SERDES Specifications

I have some questions.

Q1

Which specification in the datasheet should I refer to for this use case?

I think the following specification applies:

"fHSDR, data rate without DPA: SERDES factor J = 2, using DDR registers, 500 Mbps"

Is my understanding correct?

Q2

The following specification is the same for all FPGA speed grades:

"fHSDR, data rate without DPA: SERDES factor J = 2, using DDR registers, 500 Mbps"

Does this mean that the supported data rate does not increase even when a faster speed grade is selected?

Q3

I am also checking the clock-rate specification. For speed grade -6, the maximum clock rate is specified as 500 MHz.

If data is received at double data rate relative to the clock, I would expect the data rate to be 1,000 Mbps, calculated as 500 MHz x2.

Why is the data rate specified as 500 Mbps instead of 1,000 Mbps?

Best regards,

Hachiware.