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Altera_Forum's avatar
Altera_Forum
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14 years ago

if statment issue

hello i am a newbie at vhdl as well as say programming. I am facing issue which is very minor for u all to decide consider i have a std_logic_vector 35 bits long and i want to check whether its...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Does this mean that i have to use clock in any code htat i write? I thoguht its just a simple code and assingment of inputs to outputs...