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Altera_Forum's avatar
Altera_Forum
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14 years ago

if statment issue

hello i am a newbie at vhdl as well as say programming. I am facing issue which is very minor for u all to decide consider i have a std_logic_vector 35 bits long and i want to check whether its...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

the problem is din0'length is 35

35-1 = 34.

So you're asking for (34 downto 32), which is 3 bits not 2.

Also, you are missing a load of signals from your process sensitivity list. This code will not simulate at all.

And why are you not using the clock? This code is going to create latches (which are bad).