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Altera_Forum
Honored Contributor
14 years agoif statment issue
hello i am a newbie at vhdl as well as say programming. I am facing issue which is very minor for u all to decide consider i have a std_logic_vector 35 bits long and i want to check whether its...
Altera_Forum
Honored Contributor
14 years agoI am trying to build a 4x4 cross bar which i will use in a switch datapth. Here is the cross bar code:
library ieee; use ieee.std_logic_1164.all; entity cross_bar is port( -- clk,rst : in std_logic; din0,din1,din2,din3 : in std_logic_vector(34 downto 0); grant0,grant1,grant2,grant3 : in std_logic_vector(1 downto 0); dout0,dout1,dout2,dout3 : out std_logic_vector(34 downto 0) -- req0,req1,req2,req3 : out std_logic_vector(1 downto 0) ); end cross_bar; architecture cross_arc of cross_bar is begin process begin if (din0(din0'length-1 downto 32) = "00") then if (grant0 = "00") then dout0 <= din0; elseif (grant1 = "01") then dout1 <= din0; elseif (grant2 = "10") then dout2 <= din0; else (grant3 = "11") then dout3 <= din0; end if; end if; end process; end cross_arc; I am mad. Cant figure it out from last 2 hours. :(