Hi, on the DE1 SoC FPGA board I'm writing from HPS/Linux to /dev/mem to the FPGA, on the FPGA I increment the value and put it back to be read from HPS/Linux. First I had everything running over h2f_lw_axi_master (HPS site in Qsys), see picture: http://www.alteraforum.com/forum/attachment.php?attachmentid=9605&stc=1 This worked. Since I also have some control commands, I now want to use h2f_axi_master for the data operation as it was, but have the control commands over the h2f_lw_axi_master interface at the HPS. I connected it that way (as I think) under QSYS, see picture: http://www.alteraforum.com/forum/attachment.php?attachmentid=9606&stc=1 This currently does not work. In SignalTap I can see, the control command "start" still arrives - it still has the same connection via the lw bridge, but everything over the "full" h2f bridge never arrives at the FPGA. I set both bridges to 32bit, never changed that. Q: What am I doing wrong here? Which setting in the HPS configs I still need to activate? Is "/dev/mem" on the linux site even the correct interface for both or shouldn't I have 2 devices, e.g. /dev/mem and /dev/mem1 or the like?! Does it make sense even for AVALONMM to use h2f_axi_master or is it better to be used only for AVALON ST?

Something looks odd with the slave ports for the input_0 and output_0 cores. The start and end addresses are the same which shouldn't be possible since even if you had only mapped a single byte that would still cause the end address to be larger than the start. I can't comment on Avalon-MM vs Avalon-ST since I'm not sure what you are trying to achieve in this design or what these custom cores do.

--- Quote Start --- Something looks odd with the slave ports for the input_0 and output_0 cores. The start and end addresses are the same which shouldn't be possible since even if you had only mapped a single byte that would still cause the end address to be larger than the start. --- Quote End --- Thank you for your answer! Unfortunately the example with the lw bridge works. The other does not. So I doubt it has to do with the addresse ends (?) It should be Avalon MM Slave, on both bridges and the HPS should make the master for both. Is ther nothing that I could check in the HPS configuration? That I need to enable something to activate the master AXI bridge on the DE1 SoC board?

You might have been getting lucky with the "working" solution. It might be that it just so happens that the decoding logic worked in your favor and it worked previously. I have never seen Qsys let you have a 0 byte address span before so I have no idea what the fabric is going to do in that case. Are those two cores exposing address lines? I'm familar with the Qsys address decoder implementation and if that span of 0 is being used to generate the decoder logic then I don't think it'll decode properly... in short I'm surprised it ever worked for you. I'm not sure what has to be done on the software side in terms of API calls but for a bridge to be active these need to occur: 1) The bridge needs to recieve an active clock from the clock manager (and the FPGA clock as well for the other side to work) 2) The bridge needs to be mapped into the address space, by default neither H2F bridge is mapped 3) The bridge needs to be taken out of reset (and the FPGA side as well) If you were able to get transactions through the lightweight bridge then I expected the above to already be taken care of in software for the H2F bridge as well. I think any time you configure the FPGA from the HPS the steps above are taken care of as well. The base address you access is different for the H2F bridge which is located at physical address 0xC000_0000, the lightweight bridge you were accessing before is much higher up in the address space. Perhaps your accesses are still being sent to the lightweight bridge.

Great answer, so far! Well, the c000... addresses my QSYS does not accept, it says it's outside. However I could adjust the end addresses for the "input" and "output" component. Basically, now I understand, "control" has width 3, since there are 3 different 1bit signals. "input" consists of an 8bit writedata and a 1bit write signal, so I gave 9. Similar to output, with read. The numbers are fine now, but the result is the same - the bridge seems still dead. And still, I don't know why I needed to adjust (I did on the component: "Edit" -> "Interfaces" -> "Explicit address span" to "00000000000000000009" from an all 0 line. I don't understand why control is keeping this all 0 entry, but the 3 bit can be summed up correctly. https://www.alteraforum.com/forum/attachment.php?attachmentid=9613 I remember certain bridges can be turned on/off even by uboot. BTW. I turned them all on (uboot: run bridge_enable_handoff), no result. Any further ideas?

EDIT: I found my mistake, the C program had the wrong address. Using the lw address I was listening on the main axi bridge and never received anything.

HPS: h2f_lw_axi_master and h2f_axi_master | Altera Community

11 Replies

Altera_Forum
Honored Contributor
11 years ago
Something looks odd with the slave ports for the input_0 and output_0 cores. The start and end addresses are the same which shouldn't be possible since even if you had only mapped a single byte that would still cause the end address to be larger than the start.

I can't comment on Avalon-MM vs Avalon-ST since I'm not sure what you are trying to achieve in this design or what these custom cores do.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Something looks odd with the slave ports for the input_0 and output_0 cores. The start and end addresses are the same which shouldn't be possible since even if you had only mapped a single byte that would still cause the end address to be larger than the start.

--- Quote End ---

Thank you for your answer! Unfortunately the example with the lw bridge works. The other does not. So I doubt it has to do with the addresse ends (?)
It should be Avalon MM Slave, on both bridges and the HPS should make the master for both.

Is ther nothing that I could check in the HPS configuration? That I need to enable something to activate the master AXI bridge on the DE1 SoC board?
Altera_Forum
Honored Contributor
11 years ago
You might have been getting lucky with the "working" solution. It might be that it just so happens that the decoding logic worked in your favor and it worked previously. I have never seen Qsys let you have a 0 byte address span before so I have no idea what the fabric is going to do in that case. Are those two cores exposing address lines? I'm familar with the Qsys address decoder implementation and if that span of 0 is being used to generate the decoder logic then I don't think it'll decode properly... in short I'm surprised it ever worked for you.

I'm not sure what has to be done on the software side in terms of API calls but for a bridge to be active these need to occur:

1) The bridge needs to recieve an active clock from the clock manager (and the FPGA clock as well for the other side to work)
2) The bridge needs to be mapped into the address space, by default neither H2F bridge is mapped
3) The bridge needs to be taken out of reset (and the FPGA side as well)

If you were able to get transactions through the lightweight bridge then I expected the above to already be taken care of in software for the H2F bridge as well. I think any time you configure the FPGA from the HPS the steps above are taken care of as well. The base address you access is different for the H2F bridge which is located at physical address 0xC000_0000, the lightweight bridge you were accessing before is much higher up in the address space. Perhaps your accesses are still being sent to the lightweight bridge.
Altera_Forum
Honored Contributor
11 years ago
Great answer, so far! Well, the c000... addresses my QSYS does not accept, it says it's outside. However I could adjust the end addresses for the "input" and "output" component. Basically, now I understand, "control" has width 3, since there are 3 different 1bit signals. "input" consists of an 8bit writedata and a 1bit write signal, so I gave 9. Similar to output, with read. The numbers are fine now, but the result is the same - the bridge seems still dead. And still, I don't know why I needed to adjust (I did on the component: "Edit" -> "Interfaces" -> "Explicit address span" to "00000000000000000009" from an all 0 line. I don't understand why control is keeping this all 0 entry, but the 3 bit can be summed up correctly.

https://www.alteraforum.com/forum/attachment.php?attachmentid=9613

I remember certain bridges can be turned on/off even by uboot. BTW. I turned them all on (uboot: run bridge_enable_handoff), no result.

Any further ideas?
Altera_Forum
Honored Contributor
11 years ago
EDIT: I found my mistake, the C program had the wrong address. Using the lw address I was listening on the main axi bridge and never received anything.
Altera_Forum
Honored Contributor
11 years ago
You only have indirect control over the end address. The way it works is you expose slave address bits which Qsys uses to determine the span the slave port takes up in the memory map. When you enter the slave ports base address the end address moves with it so you don't have direct control over that field. The end address = <base address> + <slave span> - 1. I didn't realize your components were a single 8-bit location so that's why the start and end address is the same (span is 1 which cancels out the -1 in that calculation).
Altera_Forum
Honored Contributor
11 years ago
Great answer, thank you very much!
Altera_Forum
Honored Contributor
11 years ago
HI,

I work on DE1-Soc. I am using a linux BSP (linux console) that i found in terasic's website linux image.

I have some questions about the AXI bridge. In fact i would like to send some data from the hps to the fpga through the AXI bridge ( HPS-to-FPGA AXI ) and then use those data by the FPGA. I created a Quartus project based on the DE1-SOC-GHRD. The DE1-SOC-GHRD includes the file soc_system.qsys which includes hps_0 (HPS component). I would like to use the EPCQ to store the fpga configuration (.sof) And sD card for linux and my app.

Can you give me some advices about how to use the AXI bridge? work to do for the FPGA and work to do for processor?

I am new in Soc, and i found it hard to understand how it works. I read cyclone V handbook but i feel that i missed something and i don't know what.

Thank you for your help.

PS: sorry for my bad english
Altera_Forum
Honored Contributor
11 years ago
Hi, let me answer in a quite general way, perhaps this will help you more. Have a look into the following tutorial. It's about 10 pages and will give you a good insight of how to work with SoC FPGAs, QSYS, AXI Bridge, Testbench and debugging with Logic Analyzer - these techniques IMHO are the bare minimum, but it's worth it. BTW the examples are for the ARROW SoCKIT and in Verilog, I did it with another Cyclone V board, w/o big deal.

http://zhehaomao.com/blog/fpga/2013/12/22/sockit-1.html
Altera_Forum
Honored Contributor
11 years ago
HI, Thank you very much for your replay!! It's great tutorial.

I did a small project. I access pio led of the FPGA through the h2f_lw_axi_master. The lightweight bridge’s region of memory begins at address 0xff200000. Now I m trying to access FPGA pio led through h2f_axi_master but I did not find the base address!!

Do you have any idea?!

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HPS: h2f_lw_axi_master and h2f_axi_master

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