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Something looks odd with the slave ports for the input_0 and output_0 cores. The start and end addresses are the same which shouldn't be possible since even if you had only mapped a single byte that would still cause the end address to be larger than the start.
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Thank you for your answer! Unfortunately the example with the lw bridge works. The other does not. So I doubt it has to do with the addresse ends (?)
It should be Avalon MM Slave, on both bridges and the HPS should make the master for both.
Is ther nothing that I could check in the HPS configuration? That I need to enable something to activate the master AXI bridge on the DE1 SoC board?
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