Global Clock & Regional clock inputs in Agilex M FPGA

Hi,

Kindly answer the following query related to USB PHY connection to MAX10 in Agilex I series FPGA design.

In the reference design, why USB phy is connected to BMC(MAX10) in PCIe based card based on Agilex I FPGA design.

What can be done using USB interface in the the design. 

Regards,

Thulasi