HPS: h2f_lw_axi_master and h2f_axi_master

Great answer, so far! Well, the c000... addresses my QSYS does not accept, it says it's outside. However I could adjust the end addresses for the "input" and "output" component. Basically, now I understand, "control" has width 3, since there are 3 different 1bit signals. "input" consists of an 8bit writedata and a 1bit write signal, so I gave 9. Similar to output, with read. The numbers are fine now, but the result is the same - the bridge seems still dead. And still, I don't know why I needed to adjust (I did on the component: "Edit" -> "Interfaces" -> "Explicit address span" to "00000000000000000009" from an all 0 line. I don't understand why control is keeping this all 0 entry, but the 3 bit can be summed up correctly.