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Altera_Forum
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11 years ago

HPS: h2f_lw_axi_master and h2f_axi_master

Hi, on the DE1 SoC FPGA board I'm writing from HPS/Linux to /dev/mem to the FPGA, on the FPGA I increment the value and put it back to be read from HPS/Linux. First I had everything running over h2f_...
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Altera_Forum
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11 years ago

You only have indirect control over the end address. The way it works is you expose slave address bits which Qsys uses to determine the span the slave port takes up in the memory map. When you enter the slave ports base address the end address moves with it so you don't have direct control over that field. The end address = <base address> + <slave span> - 1. I didn't realize your components were a single 8-bit location so that's why the start and end address is the same (span is 1 which cancels out the -1 in that calculation).