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Altera_Forum
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11 years ago

HPS: h2f_lw_axi_master and h2f_axi_master

Hi, on the DE1 SoC FPGA board I'm writing from HPS/Linux to /dev/mem to the FPGA, on the FPGA I increment the value and put it back to be read from HPS/Linux. First I had everything running over h2f_...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Something looks odd with the slave ports for the input_0 and output_0 cores. The start and end addresses are the same which shouldn't be possible since even if you had only mapped a single byte that would still cause the end address to be larger than the start.

I can't comment on Avalon-MM vs Avalon-ST since I'm not sure what you are trying to achieve in this design or what these custom cores do.