How to use Signal tab to verify signal PHY Lite for Parallel Interfaces FPGA IP

You are most likely tapping a post-fit node in your design that cannot be tapped. Look over the Node List in your Signal Tap file and see if you can tap either a pre-synthesis version of the node or another signal that feeds into the node you want to look at.

Another suggestion is to follow the PHYlite hardware simulation in https://www.intel.com/content/www/us/en/docs/programmable/683384/current/an-747-altera-phylite-for-parallel-interfaces.html

Since this is something we already developed and works.

Here is the second examples https://www.intel.com/content/www/us/en/docs/programmable/683231/current/to-design-example.html

Thanks

Is there further question? If no, we shall close this thread.

Hi Kenny_Tan
Thanks for your reply.
I am new. The examples you shared are quite brief about using signal tab
Please send me a tutorial or step by step example on using signal tab for arria 10

Here you go, https://www.youtube.com/watch?v=R8vUERKTDzg

I attached a screenshot below for you to take note on the postfitsignaltap. You should watch the video completely.

Hi Kenny_Tan,
Thank for reply.
You can close this thread