Forum Discussion
New ContributorHow to Simulate the ADC IP from MAX 10
Hi,
I want to simulate the ADC IP. I have generated a qsys file
and then I have generated the Synthesis and Simulations files (both VHDL) in Quartus Prime Lite
I have set the simulator to Questa Intel FPGA and also VHDL, and added my test Bench (also VHDL)
then i start the simulation:
Tools--> Run Simulation Tool--> RTL Simulation
Its compiling, but then I get these errors.
it seems that either some settings are wrong in the Simulation files from the ADC IP, or an library include is missing. I have no idea how to fix it.
The ADC block works in the synthesis on the Hardware.
I also get 2 warnings in the IP files during compilation:
** Warning: (vlog-2083) d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel/submodules/fiftyfivenm_adcblock_top_wrapper.v(11): Carriage return (0x0D) is not followed by a newline (0x0A).
** Warning: d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel/submodules/altera_merlin_master_translator.sv(536): (vlog-13528) Extra Parentheses after time system function.
I have tried to simalate a none qsys IP block (FIFO) and this worked as expected.
Used Software:
Quartus Prime Lite 24.1 (because the 25.1 has problems with the PLL IP, but the same error message during Simulation)
Questa Intel Starter FPGA Edition 2024.3
Kind Regrards
Jonas
15 Replies
JonasI have run the
msim_setup.tcl
and then switch to my
TB_ADC_to_Parallel_run_msim_rtl_vhdl.do
file same result.
is this possible with the Quartus Prime Light /Quasta Altera Starter version?
KennyT_alteraSuper Contributor
Is there any further queries?
- Jonas
I had no time to look into it (other parts of the project are more urgent at the moment)
I will report back if I tried your last suggestions
- KennyT_altera
Sorry for the late reply.
When I checked the TB_ADC_to_Parallel_run_msim_rtl_vhdl.do file, I noticed that its content is incorrect:
vlib ADC_to_Parallel vmap ADC_to_Parallel ADC_to_Parallel vlog -work ADC_to_Parallel +incdir+d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel {d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel/adc_to_parallel.v} ]
If you have already run the msim_setup.tcl script, you only need to proceed with commands like dev_com, com, etc. You may refer to the documentation for further details: https://docs.altera.com/r/docs/683870/25.3.1/quartus-prime-pro-edition-user-guide-third-party-simulation/questasim-simulation-setup-script-example
3.4. QuestaSim Simulation Setup Script Example
- Jonas
Thx for the Quick answer.
I Tried the way over the msim_setup.tcl with the same result. Also, all the compile commands are in the automatically generated do file.
What I have found is when I strip the Project down to the QSYS and TB only and then port it to Verilog it works (but only in Quartus Prime Lite 25.1. 24.1 starts the simulation and the hangs)when I then back port to VHDL I have the original issue.
I think the problem is that the ADC IP generates only Verilog files that there is some problem with the VHDL vs Verilog Library’s. Or the Mixed Language Sim is not setup properly.the VHDL sim command:
vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L rtl_work -L work -L ADC_to_Parallel -voptargs="+acc" TB_ADC_to_Parallel2the Verilog sim command:
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L rtl_work -L work -L ADC_to_Parallel -voptargs="+acc" TB_ADC_to_Parallel2
Verilog and VHDL seams to need different library’s
when I use the Verilog vsim command line I get other errorsBut the simulation is starting but the interface between the Verilog and VHDL files seems to not working. I think because the now needed VHDL library from the interface is missing.
So how do I Setup an Proper mixt language simulation?
the documentation says even the Started Edition support it. But I where, up to now, unable to find an example or tutorial.We use VHDL in our Company so a Verilog only Desing is only the last resort.
Kind Regards
Jonas- KennyT_altera
can you attached your design here to take a look?
- Jonas
this is not the original file (which I cannot share)
but a minimalistic case with the same error
ChrisR_AlteraOccasional Contributor
Make sure you are generating the simulation files and testbench in Platform Designer?
In your testbench folder, you should have sim/mentor/msim_setup.tcl. Open that and you should see a top level template (TOP-LEVEL TEMPLATE - BEGIN/END). Take the template and make a mentor.do file and edit with your files/options. Using this template will make sure all the required libraries are being added (and hopefully fixing your issue)
