How to Simulate the ADC IP from MAX 10

Hi,

I want to simulate the ADC IP. I have generated a qsys file  

and then I have generated the Synthesis and Simulations files (both VHDL) in Quartus Prime Lite

I have set the simulator to Questa Intel FPGA and also VHDL,  and added my test Bench (also VHDL)

then i start the simulation:
Tools--> Run Simulation Tool--> RTL Simulation 

Its compiling, but then I get these errors.

it seems that either some settings are wrong in the Simulation files from the ADC IP, or an library include is missing. I have no idea how to fix it.
The ADC block works in the synthesis on the Hardware.

I also get 2 warnings in the IP files during compilation:
** Warning: (vlog-2083) d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel/submodules/fiftyfivenm_adcblock_top_wrapper.v(11): Carriage return (0x0D) is not followed by a newline (0x0A).

** Warning: d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel/submodules/altera_merlin_master_translator.sv(536): (vlog-13528) Extra Parentheses after time system function.

I have tried to simalate a none qsys IP block (FIFO) and this worked as expected.

Used Software:

Quartus Prime Lite 24.1 (because the 25.1 has problems with the PLL IP, but the same error message during Simulation)
Questa Intel Starter FPGA Edition 2024.3

Kind Regrards

Jonas