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Jonas's avatar
Jonas
Icon for New Contributor rankNew Contributor
3 months ago

How to Simulate the ADC IP from MAX 10

Hi, I want to simulate the ADC IP. I have generated a qsys file   and then I have generated the Synthesis and Simulations files (both VHDL) in Quartus Prime Lite I have set the simulator to Qu...
Programmable Logic Device
ChrisR_Altera's avatar
ChrisR_Altera
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Make sure you are generating the simulation files and testbench in Platform Designer? 

https://docs.altera.com/r/docs/683609/26.1/quartus-prime-pro-edition-user-guide-platform-designer/generating-simulation-files-for-platform-designer-systems-and-ip-variants

In your testbench folder, you should have sim/mentor/msim_setup.tcl.   Open that and you should see a top level template (TOP-LEVEL TEMPLATE - BEGIN/END).   Take the template and make a mentor.do file and edit with your files/options. Using this template will make sure all the required libraries are being added (and hopefully fixing your issue)

https://docs.altera.com/r/docs/683870/25.3.1/quartus-prime-pro-edition-user-guide-third-party-simulation/sourcing-questasim-simulator-setup-scripts