New Contributor
Super Contributorcan you attached your design here to take a look?
New Contributorthis is not the original file (which I cannot share)
but a minimalistic case with the same error
Super ContributorThanks for attaching design,
Platform designer usually run with msim_setup.tcl
I did not see that in your design, can you follow the steps above and create one?
New ContributorThere is an msim_setup.tcl file it is in the
\ADC_to_Parallel\simulation\mentor
subfolder, this get generated when I Perform Generate->Generate HDL in the Platform Designer.
Why do I need manual creation when the Verilog version does't need this? Should this not be Generated by the Navlink when I do Tools-> Runs Simulation Tools--> RTL Simulation in Quartus Prime Light
The simulation command from msim_setup.tcl script should be inside the TB_ADC_to_Parallel_run_msim_rtl_vhdl.do file.
And where should I run the
ip-setup-simulation --quartus-project=ADC_to_Parallel.qpf command?
when I run this on the CMD console nothing happens. I get a short opening from a commanding window which closes immediately and no report on the starting command line window.
the Tools--> Lunch Simulation Compiler won’t acespt the path to the vsim command
Super ContributorThe Nativelink created is not intended for Platform Designer usage; it is usually for designs without PD. I will take a look at the msim_setup.tcl and get back to you.
