IO Placement issue when using HPS EMIF (1SX165HN3F43E2VG)

Question

Hello everyone,&nbsp;I encountered an issue when assigning a simple GPIO to Bank M, where the HPS EMIF is connected. I would like to know whether it is possible to use I/Os on this bank while the HPS EMIF is enabled.Everything works as expected as long as the following pin assignment is not present:set_location_assignment PIN_P30 -to SE_IN[0]As soon as this assignment is added, the issue occurs, where SE_IN is an INPUT.Could you please let me know if using GPIOs on Bank M is supported when the HPS EMIF is configured?&nbsp;Regards,Andreas

kianhint_altera · Answer

Hi Andreas,
&nbsp;
There is some restriction on Stratix 10 IO banks with HPS EMIF due to hardwired connections. I would suggest to look at this guide here
https://docs.altera.com/r/docs/683741/24.1/external-memory-interfaces-stratix-10-fpga-ip-user-guide/restrictions-on-i/o-bank-usage-for-stratix-10-emif-ip-with-hps
&nbsp;

&nbsp;
Thanks
Regards
Kian
&nbsp;
&nbsp;

Forum Discussion

IO Placement issue when using HPS EMIF (1SX165HN3F43E2VG)

1 Reply

Recent Discussions

IO Placement issue when using HPS EMIF (1SX165HN3F43E2VG)

Agilex 3: VCCBAT pin for the battery-backed key storage.

ALTPLL - BANDWIDTH OPTION ?

MAX 10 PLL Inverted Output Timing Inquiry

EP4CE22F 256 net length report not found