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Jonas's avatar
Jonas
Icon for New Contributor rankNew Contributor
1 month ago

How to Simulate the ADC IP from MAX 10

Hi, I want to simulate the ADC IP. I have generated a qsys file   and then I have generated the Synthesis and Simulations files (both VHDL) in Quartus Prime Lite I have set the simulator to Qu...
Programmable Logic Device
Jonas's avatar
Jonas
Icon for New Contributor rankNew Contributor
1 month ago

I have run the 

msim_setup.tcl

and then switch to my

TB_ADC_to_Parallel_run_msim_rtl_vhdl.do

file same result.

is this possible with the Quartus Prime Light /Quasta Altera Starter version?

KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
21 days ago

Sorry for the late reply.

When I checked the TB_ADC_to_Parallel_run_msim_rtl_vhdl.do file, I noticed that its content is incorrect:

vlib ADC_to_Parallel vmap ADC_to_Parallel ADC_to_Parallel vlog  -work ADC_to_Parallel +incdir+d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel {d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel/adc_to_parallel.v} ]

 

If you have already run the msim_setup.tcl script, you only need to proceed with commands like dev_com, com, etc. You may refer to the documentation for further details: https://docs.altera.com/r/docs/683870/25.3.1/quartus-prime-pro-edition-user-guide-third-party-simulation/questasim-simulation-setup-script-example

3.4. QuestaSim Simulation Setup Script Example