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Jonas's avatar
Jonas
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3 months ago

How to Simulate the ADC IP from MAX 10

Hi, I want to simulate the ADC IP. I have generated a qsys file   and then I have generated the Synthesis and Simulations files (both VHDL) in Quartus Prime Lite I have set the simulator to Qu...
Programmable Logic Device
Jonas's avatar
Jonas
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2 months ago

I have run the 

msim_setup.tcl

and then switch to my

TB_ADC_to_Parallel_run_msim_rtl_vhdl.do

file same result.

is this possible with the Quartus Prime Light /Quasta Altera Starter version?

KennyT_altera's avatar
KennyT_altera
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1 month ago

Is there any further queries?

  • Jonas's avatar
    Jonas
    Icon for New Contributor rankNew Contributor
    1 month ago

    I had no time to look into it (other parts of the project are more urgent at the moment)
    I will report back if I tried your last suggestions

    • KennyT_altera's avatar
      KennyT_altera
      Icon for Super Contributor rankSuper Contributor
      1 month ago

      Noted, with thanks. 

    • KennyT_altera's avatar
      KennyT_altera
      Icon for Super Contributor rankSuper Contributor
      1 month ago

      Not sure if you have some update for the above?

    • KennyT_altera's avatar
      KennyT_altera
      Icon for Super Contributor rankSuper Contributor
      1 month ago

      As we do not receive any response from you on the previous answer that we have provided. We will close the case for now.