How to make bidirectional bus in SystemVerilog

Most likely a connection error, but you did not show enough code that might give a hint at what is wrong. How are you driving the bus in your testbench and CPLD? You need to be using a continuous assignment in both places. Either

Here is what I am trying to do (simplified and with extraneous fluff removed). Basically I have a multiplexed 8 bit address/data bus. I want to latch an address (0 or 1) and then write data to some output bits depending on the address (this seems to work just fine in the test bench when I simulate in Modelsim). Then I want to read the state of some input bits (this is the part that I can never see on the bidirectional bus in the simulator).

It would help if you attached the example code you are trying to model, what you wrote would not even compile.

No.

I only see the value from the lower module at the cpldbus. That value never drives the cpubus. At the time when I see cpldbus driving '8h33 the cpubus is showing tristate, which is the "value" it gets from the assign statement when both ale and wr are false.

Your code is not legal. Apparently the simulator version you are using is not catching the error and producing incorrect results. You cannot connect a variable to an inout port, only wires are allowed to be connected to inout ports. Change the declaration of cpubus in module test to

wire  cpubus;

your code

module top (
        inout wire   cpldbus,
        input bit           ale,
        input bit           rd,
        input bit           wr,
        output reg  outbit,
        input reg   inbit );
   
   logic                addr;
   logic                data;
   
   always_ff @ (posedge ale, posedge wr)
     begin
    if (ale) addr = cpldbus; // when ale is true latch the address
    if (wr)
      begin
         if (addr == 0) outbit = cpldbus;
         if (addr == 1) outbit = cpldbus;
      end
     end
   
   assign# 1ps cpldbus = (rd) ? data : 8'bZ;
   
   always_ff @ (posedge rd)
     begin
    if (addr == 2) data = inbit;
    if (addr == 3) data = inbit;
     end
   
endmodule
module test ();
   
   localparam time PERIOD = (1.0e9/14.7456e6)*1ns;
   
   wire         cpubus;
   
   bit            ale;
   bit            rd;
   bit            wr;
   reg         outbit;
   reg         inbit;
   
   logic  data;
   
   // DUT
   top u1(
      .cpldbus(cpubus),
      .ale,
      .rd,
      .wr,
      .outbit,
      .inbit
      );
   
   initial
     begin
    // put some dummy data on inbit
    inbit = 8'h33;
    // Stimulus
    //$stop; // to allow signal setup on wave page
    
    // Write A5 to addr 0
   # PERIOD data = 0;
   # PERIOD ale = 1;
   # PERIOD ale = 0;
   # PERIOD data = 8'hA5;
   # PERIOD wr = 1;
   # PERIOD wr = 0;
    
    // Write 5A to addr 1
   # PERIOD data = 1;
   # PERIOD ale = 1;
   # PERIOD ale = 0;
   # PERIOD data = 8'h5A;
   # PERIOD wr = 1;
   # PERIOD wr = 0;
    
    // Read addr 2
   # PERIOD data = 2;
   # PERIOD ale = 1;
   # PERIOD ale = 0;
   # PERIOD rd = 1;
   # PERIOD rd = 0;
     end
   assign# 1ps cpubus = (ale || wr) ? data : 8'bZ;
   
endmodule 

Thanks dave_59. Your pointers worked. Also the delays to solve the race condition is great. But that only affects the simulation, not the actual hardware that is created, right? Of course it is important to simulate what will really happen in the hardware.

always_ff @ (negedge ale)
  addr = cpldbus;
always_ff @ (negedge wr)
begin
  if (addr == 0) outbit = cpldbus;
  if (addr == 1) outbit = cpldbus;
end

You probably want to use always_latch as that is closer to the actual behavior. It's OK if cpldbus has not stabilized, the block will continue to execute passing the value on to outbit.