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Honored Contributor
Honored ContributorHow to make bidirectional bus in SystemVerilog
I have a bidirectional 8 bit bus for communicating between my CPLD and my main CPU. At the top level module I declared this like this (left out details of other IO stuff): module top ( inout [7...
Altera_ForumHonored Contributor
Honored ContributorI only see the value from the lower module at the cpldbus. That value never drives the cpubus. At the time when I see cpldbus driving '8h33 the cpubus is showing tristate, which is the "value" it gets from the assign statement when both ale and wr are false.
Is there something else one needs to do to implement a bidirectional bus?
