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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to make bidirectional bus in SystemVerilog

I have a bidirectional 8 bit bus for communicating between my CPLD and my main CPU. At the top level module I declared this like this (left out details of other IO stuff): module top ( inout [7...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Most likely a connection error, but you did not show enough code that might give a hint at what is wrong. How are you driving the bus in your testbench and CPLD? You need to be using a continuous assignment in both places. Either

assign gpbus = wr ? data : 8'z;

or

assign gpbus = data;

And you procedurally assign data to 8'bz when that side is not driving.