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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to make bidirectional bus in SystemVerilog

I have a bidirectional 8 bit bus for communicating between my CPLD and my main CPU. At the top level module I declared this like this (left out details of other IO stuff): module top ( inout [7...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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You probably want to use always_latch as that is closer to the actual behavior. It's OK if cpldbus has not stabilized, the block will continue to execute passing the value on to outbit.

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Now that confuses me a bit. I thought that each of those constructs would create different hardware. always_latch would create level sensitive gates and always_ff would create edge sensitive gates. Am I way off base there?