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Honored Contributor
Honored ContributorHow to make bidirectional bus in SystemVerilog
I have a bidirectional 8 bit bus for communicating between my CPLD and my main CPU. At the top level module I declared this like this (left out details of other IO stuff): module top ( inout [7...
Altera_ForumHonored Contributor
Honored ContributorIt would help if you attached the example code you are trying to model, what you wrote would not even compile.
You need to make sure the testbench is driving Z's when you want to read what the device is driving, and the device must be driving Z's to read what the testbench is driving. Dave
