How to make bidirectional bus in SystemVerilog

I have a bidirectional 8 bit bus for communicating between my CPLD and my main CPU. At the top level module I declared this like this (left out details of other IO stuff):

module top ( inout [7:0] gpbus, input bit rd, input bit wr );

When I drive the gpbus from my test bench it works fine. When I set the gpbus to 8'bZ it does tri-state it. However, when I drive it from inside my module nothing changes at the test bench. It stays tri-stated.

How do I correctly create and connect such a bus and simulate it? I've tried using the alias statement but no matter what I do that creates an error "near text 'alias' expecting endmodule".