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Altera_Forum
Honored Contributor
Honored ContributorHow to make bidirectional bus in SystemVerilog
I have a bidirectional 8 bit bus for communicating between my CPLD and my main CPU. At the top level module I declared this like this (left out details of other IO stuff): module top ( inout [7...
Altera_ForumHonored Contributor
Honored ContributorNo, you are not off base. I don't know your design intent. If the real hardware depends on delays to operate, you need to account for it in your model, either with proper delays, or choosing the correct abstraction.
