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Altera_Forum
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13 years ago

How to make bidirectional bus in SystemVerilog

I have a bidirectional 8 bit bus for communicating between my CPLD and my main CPU. At the top level module I declared this like this (left out details of other IO stuff): module top ( inout [7...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

No.

When only the top module is driving, you should see the driven value.