How to make bidirectional bus in SystemVerilog

Your code is not legal. Apparently the simulator version you are using is not catching the error and producing incorrect results. You cannot connect a variable to an inout port, only wires are allowed to be connected to inout ports. Change the declaration of cpubus in module test to

wire  cpubus;

Then cpubus will always show the resolved value.

Also, there may be a race in your testbench because you change wr and cpubus simultaneously. You should be a delay in your continuous assignments.

P.S. You can wrap your code with

your code

and your indentation will be preserved.

module top (
        inout wire   cpldbus,
        input bit           ale,
        input bit           rd,
        input bit           wr,
        output reg  outbit,
        input reg   inbit );
   
   logic                addr;
   logic                data;
   
   always_ff @ (posedge ale, posedge wr)
     begin
    if (ale) addr = cpldbus; // when ale is true latch the address
    if (wr)
      begin
         if (addr == 0) outbit = cpldbus;
         if (addr == 1) outbit = cpldbus;
      end
     end
   
   assign# 1ps cpldbus = (rd) ? data : 8'bZ;
   
   always_ff @ (posedge rd)
     begin
    if (addr == 2) data = inbit;
    if (addr == 3) data = inbit;
     end
   
endmodule
module test ();
   
   localparam time PERIOD = (1.0e9/14.7456e6)*1ns;
   
   wire         cpubus;
   
   bit            ale;
   bit            rd;
   bit            wr;
   reg         outbit;
   reg         inbit;
   
   logic  data;
   
   // DUT
   top u1(
      .cpldbus(cpubus),
      .ale,
      .rd,
      .wr,
      .outbit,
      .inbit
      );
   
   initial
     begin
    // put some dummy data on inbit
    inbit = 8'h33;
    // Stimulus
    //$stop; // to allow signal setup on wave page
    
    // Write A5 to addr 0
   # PERIOD data = 0;
   # PERIOD ale = 1;
   # PERIOD ale = 0;
   # PERIOD data = 8'hA5;
   # PERIOD wr = 1;
   # PERIOD wr = 0;
    
    // Write 5A to addr 1
   # PERIOD data = 1;
   # PERIOD ale = 1;
   # PERIOD ale = 0;
   # PERIOD data = 8'h5A;
   # PERIOD wr = 1;
   # PERIOD wr = 0;
    
    // Read addr 2
   # PERIOD data = 2;
   # PERIOD ale = 1;
   # PERIOD ale = 0;
   # PERIOD rd = 1;
   # PERIOD rd = 0;
     end
   assign# 1ps cpubus = (ale || wr) ? data : 8'bZ;
   
endmodule