How to deal with this warning?

Hi josyb:

Yes, you are right! I just only need a clock output.

3ks

Jerry

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Hi GPK:

Thanks for your reminder!

This warning is killed when add the first PLL's input clk's definition.

And for the second PLL is using the internal clk as input clk, so below warnings can't be killed, isn't it?

"Warning: PLL "mypll2:inst|altpll:altpll_component|pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

Warning: PLL "mypll2:inst|altpll:altpll_component|pll" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins"

Thanks

Jerry

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If you set the compensation mode to "No Compensation" (in the MegaWizard) the warning should disappear. The effect will be that the outputs of this pll will not be aligned to the input, but that doesn't matter, does it?

Hi GPK:

Thanks for your reminder!

This warning is killed when add the first PLL's input clk's definition.

And for the second PLL is using the internal clk as input clk, so below warnings can't be killed, isn't it?

"Warning: PLL "mypll2:inst|altpll:altpll_component|pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

Warning: PLL "mypll2:inst|altpll:altpll_component|pll" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins"

Thanks

Jerry

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Hi Dears:

Below is the warning info:

"Warning: PLL cross checking found inconsistent PLL clock settings:

Warning: Clock: inst2|altpll_component|pll|clk[0] with master clock period: 20.000 found on PLL node: inst2|altpll_component|pll|clk[0] does not match the master clock period requirement: 10.000

Warning: Clock: inst2|altpll_component|pll|clk[1] with master clock period: 20.000 found on PLL node: inst2|altpll_component|pll|clk[1] does not match the master clock period requirement: 10.000

Warning: Clock: inst|altpll_component|pll|clk[0] with master clock period: 20.000 found on PLL node: inst|altpll_component|pll|clk[0] does not match the master clock period requirement: 10.000"

I am using ArriaGX, and implemented two PLLs in my project. The FPGA's input clock is 100Mhz, which input to the first PLL. The first PLL's outputs are 2 100Mhz (one for internal logic clock, another for external memory clk) clock and 1 200Mhz for SignalTapII sample clock. The sencond PLL's input clock is the first PLL's output that used for internal logic.

Thanks in advance!

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Hi,

how did you define the input clock of the pll's ?

Kind regards

GPK