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Honored Contributor
Honored ContributorHow to deal with this warning?
Hi Dears: Below is the warning info: "Warning: PLL cross checking found inconsistent PLL clock settings: Warning: Clock: inst2|altpll_component|pll|clk[0] with master clock period: 2...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi GPK: Thanks for your reminder! This warning is killed when add the first PLL's input clk's definition. And for the second PLL is using the internal clk as input clk, so below warnings can't be killed, isn't it? "Warning: PLL "mypll2:inst|altpll:altpll_component|pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input Warning: PLL "mypll2:inst|altpll:altpll_component|pll" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" Thanks Jerry --- Quote End --- If you set the compensation mode to "No Compensation" (in the MegaWizard) the warning should disappear. The effect will be that the outputs of this pll will not be aligned to the input, but that doesn't matter, does it?
