How to deal with this warning?

Hi GPK:

Thanks for your reminder!

This warning is killed when add the first PLL's input clk's definition.

And for the second PLL is using the internal clk as input clk, so below warnings can't be killed, isn't it?

"Warning: PLL "mypll2:inst|altpll:altpll_component|pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

Warning: PLL "mypll2:inst|altpll:altpll_component|pll" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins"

Thanks

Jerry