--- Quote Start ---
Hi Dears:
Below is the warning info:
"Warning: PLL cross checking found inconsistent PLL clock settings:
Warning: Clock: inst2|altpll_component|pll|clk[0] with master clock period: 20.000 found on PLL node: inst2|altpll_component|pll|clk[0] does not match the master clock period requirement: 10.000
Warning: Clock: inst2|altpll_component|pll|clk[1] with master clock period: 20.000 found on PLL node: inst2|altpll_component|pll|clk[1] does not match the master clock period requirement: 10.000
Warning: Clock: inst|altpll_component|pll|clk[0] with master clock period: 20.000 found on PLL node: inst|altpll_component|pll|clk[0] does not match the master clock period requirement: 10.000"
I am using ArriaGX, and implemented two PLLs in my project. The FPGA's input clock is 100Mhz, which input to the first PLL. The first PLL's outputs are 2 100Mhz (one for internal logic clock, another for external memory clk) clock and 1 200Mhz for SignalTapII sample clock. The sencond PLL's input clock is the first PLL's output that used for internal logic.
Thanks in advance!
--- Quote End ---
Hi,
how did you define the input clock of the pll's ?
Kind regards
GPK
Honored Contributor
